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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-30335-2E
MEMORY
FLASH MEMORY CARD
PCMCIA Rel.2/JEIDA Ver.4 conformable
MB98A808Ax-/809Ax-/810Ax-/811Ax-20
FLASH ERASABLE AND PROGRAMMABLE MEMORY CARD 256 K/512 K/1 M/2 M-BYTE s DESCRIPTION
The Fujitsu MB98A808Ax, MB98A809Ax, MB98A810Ax and MB98A811Ax are Flash electrically erasable and programmable (Flash) memory cards capable of storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin package. Internal circuit is protected by two metal panels, one at the top and bottom of the card, that help to reduce chip damage from electrostatic discharge. A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. All cards are portable and operate on low power at high speed. In accordance with the Personal Computer Memory Card International Association (PCMCIA) and Japan Electrical Industry Development Association (JEIDA) industry standard specification, Flash memory cards offer additional EEPROM memory that is used to store attribute data. The attribute memory is a Flash memory card option. (See page 2 for description of the three available options.) * * * * * Credit card size: 85.6 mm (length) x 54.0 mm (width) x 3.3 mm (thick) PCMCIA/JEIDA conformed two-piece 68-pin connector (with a two-row built-in receptacle) Single +5.0 V 5% power supply (+12.0 V 5%VPP) Command control for Write/Erase operation Write protect function
s PACKAGE
CRD-68P-M17
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s ATTRIBUTE MEMORY OPTIONS
PCMCIA and JEIDA standard memory cards from Fujitsu provide a separate EEPROM memory address space for recording fundamental card information. It is used by the card manufacturers to record basic configuration information such as device type, size, speed, etc. The attribute memory is selected by asserting the REG pin on the card interface. Option descriptions as follows:
OPTION 1: Attribute memory is not supported. REG Pin: Not Contacted
(JEIDA Ver.3 conformable) Main Memory Part Number Memory Device Attribute Memory Access Memory Device Access Time Time 200 ns 200 ns 200 ns -- -- -- -- -- -- -- -- Memory Organization * 256 K x 8 bits/128 K x 16 bits 512 M x 8 bits/256 K x 16 bits 1 M x 8 bits/512 M x 16 bits 2 M x 8 bits/1 M x 16 bits
MB98A808A1 1 M Flash Memory x 2 pcs MB98A809A1 1 M Flash Memory x 4 pcs MB98A810A1 1 M Flash Memory x 8 pcs
MB98A811A1 1 M Flash Memory x 16 pcs 200 ns
OPTION 2: Attribute memory in a separate location is not supported. When REG line is asserted, "FF" is output to the data bus to indicate that attribute data may be stored in main memory.
Main Memory Part Number Memory Device (PCMCIA Rel.2/JEIDA Ver.4 conformable) Attribute Memory Memory Organization * Access Memory Device Access Time Time 200 ns 200 ns 200 ns -- -- -- -- -- -- -- -- 256 K x 8 bits/128 K x 16 bits 512 K x 8 bits/256 K x 16 bits 1 M x 8 bits/512 K x 16 bits 2 M x 8 bits/1 M x 16 bits
MB98A808A2 1 M Flash Memory x 2 pcs MB98A809A2 1 M Flash Memory x 4 pcs MB98A810A2 1 M Flash Memory x 8 pcs
MB98A811A2 1 M Flash Memory x 16 pcs 200 ns
OPTION 3: Attribute memory is supported. The data is stored in 16 K-bit EEPROM. When the REG line is asserted, data stored in EEPROM is output to the data bus.
Main Memory Part Number Memory Device (PCMCIA Rel.2/JEIDA Ver.4 conformable) Attribute Memory Memory Organization * Access Memory Device Access Time Time 200 ns EEPROM x 1 pcs 300 ns 256 K x 8 bits/128 K x 16 bits 200 ns EEPROM x 1 pcs 300 ns 512 K x 8 bits/256 K x 16 bits 200 ns EEPROM x 1 pcs 300 ns 1 M x 8 bits/512 K x 16 bits
MB98A808A3 1 M Flash Memory x 2 pcs MB98A809A3 1 M Flash Memory x 4 pcs MB98A810A3 1 M Flash Memory x 8 pcs
MB98A811A3 1 M Flash Memory x 16 pcs 200 ns EEPROM x 1 pcs 300 ns 2 M x 8 bits/1 M x 16 bits Note: * To be configured by user. 2
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
Fig. 1 - MB98A808Ax, 809Ax, 810Ax, and 811Ax BLOCK DIAGRAM
VCC GND WE OE VPP1 VPP2 R R
R
R = 100 K
16K EEPROM *1 CS R CE1 R CE2 R REG *3 A0 A18 *2 A19 *2 A20 *2 A1 * * * A17 INPUT DECODER & BUFFER CE0 * * * * * * * CE15 11 ADD I/O OE WE
CE
OE WE I/O TRANSCEIVER & BUFFER
WP.SW
1 Mb Flash Memory x1 (MB98A808Ax) x2 (MB98A809Ax) x4 (MB98A810Ax) x8 (MB98A811Ax) ADD I/O 8
VPP
17
VPP ADD 1 Mb Flash Memory x1 (MB98A808Ax) x2 (MB98A809Ax) x4 (MB98A810Ax) x8 (MB98A811Ax) CE I/O 8
OE WE
VCC R1 = 10 K BVD1 BVD2 WP D0 * * D15 CD1 CD2 C1
Internal circuit
Notes: *1. EEPROM is only available in Option 3 (for attribute memory) Flash Memory cards. *2. See pins 47, 48, and 49 in "PIN ASSIGNMENTS." *3. N.C. terminal in MB98A8xxA1 series.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s PIN ASSIGNMENTS
MB98A808Ax MB98A809Ax MB98A810Ax MB98A811Ax Pin No. MB98A808Ax MB98A809Ax MB98A810Ax MB98A811Ax GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 *1 N.C. N.C. N.C. VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. REG/N.C. *2 BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 N.C. N.C. N.C. VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. REG/N.C. *2 BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 N.C. N.C. VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. REG/N.C. *2 BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 N.C. VCC VPP2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. REG/N.C. *2 BVD2 BVD1 D8 D9 D10 CD2 GND
*1: A18 doesn't relate with "H" and "L" level. *2: N.C. terminal in MB98A8xxA1 series. 4
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s PIN DESCRIPTIONS
Symbol A0 to A20 D0 to D15 Pin Name Address Input Data Input/Output Input/Output Input Input/Output Function Address Inputs, A0 to A20. Data Inputs/Outputs. This data bus size (8-bit or 16-bit) is selected with CE1 and CE2. Active Low. - Lower byte (D0 to D7) is selected for read/write/ erase function of flash memory cards. Active Low. - Upper byte (D8 to D15) is selected for read/write / erase function of flash memory cards. Active Low. - Attribute memory is selected for read/write function of identification data of flash memory cards. (N.C. or "FF" data or attribute data.) Active Low. - Output enable for flash memory cards. Active Low. - Write enable for flash memory cards. Programming voltage for lower byte. Programming voltage for upper byte. These pins detect if the card has been correctly inserted. Both pins are tied to GND internally. Write controller for flash memory cards. This pin outputs the Protect/Non Protect status of "WP Switch". Both pins are tied to VCC internally. Power Supply Voltage. (+5.0 V 5%) System Ground.
CE1
Card Enable for Lower Byte
Input
CE2
Card Enable for Upper Byte
Input
REG
Attribute Memory Select
Input
OE WE VPP1 VPP2 CD1, CD2 WP BVD1, BVD2 VCC GND N.C.
Output Enable Write Enable Programming Voltage 1 Programming Voltage 2 Card Detect Write Protect Battery Voltage Detect Power Supply Ground Non Connection
Input Input Input Input Output Output Output -- -- --
s PIN LOCATIONS
Fig. 2 - BOTTOM VIEW (CONNECTOR SIDE)
Front Side
34
1
68 Back Side
35
5
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s FUNCTIONAL TRUTH TABLE
MAIN MEMORY FUNCTION *1
Read Function (REG = VIH) CE2 H H H L L X CE1 H L L H L X A0 X L H X X X OE X L L L L H WE WP *2 X H H H H H X X X X X X VPP2 VPPL VPPL VPPL VPPL VPPL VPPL VPP1 VPPL VPPL VPPL VPPL VPPL VPPL Mode Standby Read (x8) Read (x8) Read (x8) Read (x16) Output Disable High-Z High-Z DOUT (Upper Byte) DOUT High-Z Data Input/Output D8 to D15 D0 to D7 High-Z WP SW P or NP
DOUT P or NP (Lower Byte) DOUT P or NP (Upper Byte) High-Z P or NP P or NP P or NP
Erase/Write/Verify Function (REG = VIH) CE2 H H H H H L L L L X CE1 H L L L L H H L L X A0 X L H L H X X X X X OE X L L H H L H L H H WE WP *2 X H H L L H L H L H X L L L L L L L L L VPP2 VPPH VPPL*3 VPPH VPPL*3 VPPH VPPH VPPH VPPH VPPH VPPH VPP1 VPPH VPPH VPPL*3 VPPH VPPL*3 VPPL*3 VPPL*3 VPPH VPPH VPPH Mode Standby Read (x8) Read (x8) Write (x8) Write (x8) Read (x8) Write (x8) Read (x16) Write (x16) Output Disable High-Z High-Z High-Z High-Z DOUT DIN DOUT DIN High-Z Data Input/Output D8 to D15 D0 to D7 DOUT DOUT DIN DIN High-Z High-Z High-Z WP SW P or NP NP NP NP NP NP NP NP NP NP
Notes: *1. H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect *2. L-level is output when WPSW = NP. H-level is output when WPSW = P. *3. VPPL is recommended though it is functionable at VPPH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY FUNCTION *1 (REG = VIL) *2 CE2 H H H H H L L L L X H H H H H L L L L X CE1 H L L L L H H L L X H L L L L H H L L X A0 X L H L H X X X X X X L H L H X X X X X OE X L L H H L H L H H X L L H H L H L H H WE X H H L L H L H L H X H H L L H L H L H WP L L L L L L L L L L H H H H H H H H H H Mode Standby Read (x8) Read (x8) Write (x8) Write (x8) Read (x8) Write (x8) Read (x16) Write (x16) Output Disable Standby Read (x8) Read (x8) Output Disable Output Disable Read (x8) Output Disable Read (x16) Output Disable Output Disable H H High-Z DOUT *3 (Lower Byte) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H High-Z H X Data Input/Output D15 to D8 High-Z DOUT *3 (Lower Byte) H DIN (Lower Byte) X High-Z High-Z DOUT *3 (Lower Byte) DIN (Lower Byte) High-Z High-Z DOUT *3 (Lower Byte) H D7 to D0 WP SW NP NP NP NP NP NP NP NP NP NP P P P P P P P P P P
Notes: *1. H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect *2. N.C. for MB98A808A1, 809A1, 810A1, and 811A1. *3. H-level is output for MB98A808A2, 809A2, 810A2, and 811A2.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s WRITE/ERASE CHIP DECODING INFORMATION
Bus Organization CE2 CE1 A23 A22 A21 L L H L L H H H L L L H 8-bit Bus H L H H L L H L H L H H L L H 16-bit Bus L L L H H Note: H = VIH, L = VIL, X = Either VIH or VIL L H L H L H L H L H L H L H L H A0 L H L H L H L H L H L H L H L H Decode Chips Chip 0 Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 Chip 7 Chip 8 Chip 9 Chip 10 Chip 11 Chip 12 Chip 13 Chip 14 Chip 15 Chip 1 Chip 3 Chip 5 Chip 7 Chip 9 Chip 11 Chip 13 Chip 15 Chip 0, Chip 1 Chip 2, Chip 3 Chip 4, Chip 5 Chip 6, Chip 7 Chip 8, Chip 9 Chip 10, Chip 11 Chip 12, Chip 13 Chip 14, Chip 15
X
X
8
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s COMMAND DEFINITION TABLE
Command Table for 8-bit Mode
Command Read Memory Read Intelligent ID Codes *4 Set Up Erase/Erase *5 Erase Verify *5 Set Up Write/Write *6 Write Verify *6 Reset *7 *8 First Bus Cycle Second Bus Cycle Bus Cycle Required Operation *1 Address *2 Data *3 Operation *1 Address *2 Data *3 1 3 2 2 2 2 2 Write Write Write Write Write Write Write RA IA ZA EA WA WA ZA 00H 90H 20H A0H 40H C0H FFH -- Read Write Read Write Read Write -- IA ZA EA WA WA ZA -- ID 20H EVD WD WVD FFH
Command Table for 16-bit Mode
Command Read Memory Read Intelligent ID Codes *4 Set Up Erase/Erase *5 Erase Verify *5 Set Up Write/Write *6 Write Verify *6 Reset *7 *8 First Bus Cycle Second Bus Cycle Bus Cycle Required Operation *1 Address *2 Data *3 Operation *1 Address *2 Data *3 1 3 2 2 2 2 2 Write Write Write Write Write Write Write RA IA ZA EA WA WA ZA 0000H 9090H 2020H A0A0H 4040H C0C0H FFFFH -- Read Write Read Write Read Write -- IA ZA EA WA WA ZA -- ID 2020H EVD WD WVD FFFFH
Notes: *1. Bus operations are defined in "FUNCTIONAL TRUTH TABLE". *2. IA = Identifier address: 00H for manufacturer code, 01H for device code. EA = Address of memory location to be read during erase verify. RA = Read Address WA = Address of memory location to be written. ZA = Address of 128 K-Byte zones involved in erase operation. Addresses are latched on the falling edge of the Write Enable pulse. *3. ID = Data read from location IA during device identification. Manufacturer = 31H for 8-bit, 3131H for 16-bit/Device = B4H for 8-bit, B4B4H for 16-bit EVD = Data read from location EA during erase verify. WD = Data to be programmed at location WA. Data is latched on the rising edge of Write Enable. WVD = Data read from location WA during write verify. WA is latched on the Write command. *4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes. *5. "ERASE FLOWCHART" in Fig.6, Fig.7 and Fig.8 illustrate the Erase Algorithm. *6. "WRITE FLOWCHART" in Fig.4 and Fig.5 illustrate the Write Algorithm. *7. The second bus cycle must be followed by the desired command register write. *8. The Reset command operates on a zone basis. To reset the entire card requires reset write cycles to each zone.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s ADDRESS CONFIGURATIONS *1 (MAIN MEMORY)
8-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIH) A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 0010 0011 1100 1101 1110 1111 CE2 H H H H H H H H CE1 L L L L L L L L D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 0 Add. 1 Add. 2 Add. 3 Add. 2,097,148 Add. 2,097,149 Add. 2,097,150 Add. 2,097,151 Add.
8-BIT BUS ORGANIZATION (CE1 = VIH, CE2 = VIL) *2 A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000X 001X 010X 011X 100X 101X 110X 111X CE2 L L L L L L L L CE1 H H H H H H H H D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 2,097,145 Add. 2,097,147 Add. 2,097,149 Add. 2,097,151 Add. D7 to D0 ----- ----- ----- ----- ----- ----- ----- -----
16-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIL) A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000X 001X 010X 011X 100X 101X 110X 111X CE2 L L L L L L L L CE1 L L L L L L L L D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 2,097,145 Add. 2,097,147 Add. 2,097,149 Add. 2,097,151 Add. D7 to D0 0 Add. 2 Add. 4 Add. 6 Add. 2,097,144 Add. 2,097,146 Add. 2,097,148 Add. 2,097,150 Add.
Notes: *1. H = VIH, L = VIL, X = Either 0 or 1. *2. Even addresses are not available in this mode.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage Input Voltage Output Voltage Programming Voltage Storage Temperature at Turning On the Power Ambient Temperature Storage Temperature Note: *1. Minimum DC input voltage is -0.5 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. *1 Note Symbol VCC VIN VOUT VPP1, VPP2 TBIAS TA TSTG Value -0.5 to +6.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -2.0 to +14.0 -10 to 70 0 to +60 -30 to +70 Unit V V V V C C C
s RECOMMENDED OPERATING CONDITIONS
Parameter VCC Supply Voltage Ground Ambient Temperature Symbol VCC GND TA Min. 4.75 -- 0 Typ. 5.0 0 -- Max. 5.25 -- +55 Unit V V C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s CAPACITANCE
Parameter Input Capacitance I/O Capacitance Notes *1 *2 Symbol CIN CI/O (TA = 25C, f = 1 MHz, VIN = VI/O = GND) Min. Max. Unit -- -- 50 50 pF pF
Notes: *1. This value does not apply to CE1, CE2, WE and REG. *2. This value does not apply to CE1, CE2, BVD1 and BVD2.
Fig. 3 - AC TEST CONDITIONS
* Input Pulse Levels: 0.6 V to 2.6 V
* Output Load
+5 V R1
* Input Pulse Rise and Fall Times: 5 ns (Transient between 0.8 V and 2.4 V) * Timing Reference Levels Input: VIL = 0.8 V, VIH = 2.4 V Output: VOL = 0.8 V, VOH = 2.0 V
DOUT (I/O) CL R2
* Including jig and stray capacitance
R1 Load I Load II 1.8 k 1.8 k
R2 990 990
CL 100 pF 5 pF
Parameter Measured All parameters except tCLZ, tOLZ, tEHQZ, tDF, tRCLZ, tROLZ, tRCHZ and tROHZ tCLZ, tOLZ, tEHQZ, tDF, tRCLZ, tROLZ, tRCHZ and tROHZ
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Notes *1 *2 Symbol ILI ILO ISB1 VCC Standby Current ISB2 VCC Active Read Current VCC Write Current VCC Erase Current VPP Leakage Current VPP Read Current or Standby Current VPP Write Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP during Read-Only Operation VPP during Write/Erase Operation Notes: *1. *2. *3. *4. *5. *4 *3 *3 *3 *3 ICC1 ICC2 ICC3 IPPS IPP1 IPP2 IPP3 VIL VIH VOL VOH VPPL VPPH Condition VCC = VCC max VIN = 0 V or VCC VCC = VCC max VIN = 0 V or VCC VCC = VCC max CE1 = CE2 = VCC -0.2 V VCC = VCC max CE1 = CE2 = VIH VCC = VCC max CE1 = CE2 = VIL cyc. = 200 ns, IOUT = 0 mA Write in progress Erase in progress VPP VCC VPP > VCC VPP VCC VPP = VPPH Write in progress VPP = VPPH Erase in progress -- -- IOL = 3.2 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min *5 -- Value Min. -- -- -- -- -- -- -- -- -- -- -- -- -0.3 2.4 -- 3.8 0 11.4 Typ. 1.0 1.0 0.9 7.0 85 2.0 10 -- 0.9 -- 9 7 -- -- -- -- -- -- Max. 20 20 1.7 14.0 125 20 30 250 1.8 250 30 30 0.8 VCC +0.3 0.4 -- 6.5 12.6 Unit A A mA mA mA mA mA A mA mA mA mA V V V V V V
This value does not apply to CE1, CE2, WE and REG. This value does not apply to BVD1, BVD2, CD1 and CD2. This value apply to VPP1 and VPP2. This value does not apply to BVD1 and BVD2. Write/Erase are inhibited when VPP = VPPL.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) MAIN MEMORY READ CYCLE *1
Parameter Read Cycle Time Card Enable Access Time Address Access Time Output Enable Access Time Card Enable to Output in Low-Z Card Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address, CE, or OE Change *2 *2 *2 *2 *3 Notes Symbol tRC tCE tACC tOE tCLZ tEHQZ tOLZ tDF tOH Min. 200 -- -- -- 5 -- 5 -- 5 Max. -- 200 200 100 -- 60 -- 60 -- Unit ns ns ns ns ns ns ns ns ns
ATTRIBUTE MEMORY READ CYCLE *1*4
Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Hold from Address Change Card Enable to Output Low-Z Output Enable to Output Low-Z Card Enable to Output High-Z Output Enable to Output High-Z *2 *2 *2 *2 Notes Symbol tRRC tRAA tRCE tROE tROH tRCLZ tROLZ tRCHZ tROHZ Min. 300 -- -- -- 5 5 5 -- -- Max. -- 300 300 150 -- -- -- 60 60 Unit ns ns ns ns ns ns ns ns ns
Notes: *1. Rise/Fall time < 5 ns. *2. Transition is measured at the point of 500 mV from steady state voltage. This parameter is specified using Load II in Fig.3. *3. This parameter is specified from the rising edge of OE, CE1 and CE2, whichever occurs first. *4. This parameter is for MB98A808A3, 809A3, 810A3, and 811A3.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH: x 8-bit Bus Organization
tRC Address (A0 to A20) VIH VIL tACC tOH VOH D0 to D7 VOL PREVIOUS DATA VALID DATA VALID
READ CYCLE 2: CE1 = VIH, CE2 = OE = VIL: x 8-bit Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization
tRC Address *1 (A1 to A20) VIH VIL tACC tOH D8 to D15 or D0 to D15 VOH PREVIOUS DATA VALID VOL DATA VALID
: Undefined
Note: *1. A0 = Either VIH or VIL.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 3: CE2 = VIH: x 8-bit Bus Organization
tRC Address (A0 to A20) VIH VIL tACC VIH CE1 VIL tCE tCLZ VIH OE VIL tOE tOH VOH D0 to D7 VOL tOLZ High-Z DATA VALID tDF tEHQZ
: Undefined
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 4: CE1 = VIH: x 8-bit Bus Organization tRC Address *1 (A1 to A20) VIH VIL tACC CE2 VIH VIL tCE tCLZ OE VIH VIL tOLZ VOH D8 to D15 VOL High-Z DATA VALID tOE tOH tDF tEHQZ
READ CYCLE 5: CE1 = CE2 = VIL: x 16-bit Bus Organization tRC Address *1 (A1 to A20) VIH VIL tACC VIH CE1 = CE2 VIL tCE tCLZ OE VIH VIL tOLZ VOH D0 to D15 VOL High-Z tOE tOH DATA VALID tDF tEHQZ
: Undefined
Note: *1. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH: x 8-bit Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization tRRC Address *2 (A0 to A11) VIH VIL tRAA tROH D0 to D7 or D0 to D15 *3 VOH PREVIOUS DATA VALID VOL DATA VALID
READ CYCLE 2: CE2 = VIH: x 8-bit Bus Organization
tRRC Address (A0 to A11) VIH VIL tRAA VIH CE1 VIL tRCE tRCLZ OE VIH VIL tROLZ VOH D0 to D7 VOL High-Z DATA VALID tROE tROH tROHZ tRCHZ
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3, and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. A0 = Either VIH or VIL during 16 bits bus organization. *3. H-level is output from D8 to D15.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 3: CE1 = CE2: x 16-bit Bus Organization
tRRC Address *2 (A1 to A11) VIH VIL tRAA VIH CE1 = CE2 VIL tRCE tRCLZ OE VIH VIL tROLZ D0 to D7 *3 VOH VOL High-Z DATA VALID tROE tROH tROHZ tRCHZ
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3, and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. A0 = Either VIH or VIL. *3. H-level is output from D8 to D15.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE/ERASE CYCLE *1 *2
Parameter Write Cycle Time Address Set Up Time Address Hold Time Data Set Up Time Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Card Enable Set Up Time before Write Card Enable Hold Time Write Enable Pulse Width Write Enable Pulse Width High Write Enable Set Up Time Write Enable Hold Time Card Enable Pulse Width Card Enable Pulse Width High Duration of Write Operation Duration of Erase Operation VPP Set Up Time to Chip Enable Low *3 *3 Notes Symbol tWC tAS tAH tDS tDH tWHGL tGHWL tCS tCH tWP tWPH tWS tWH tCP tCPH tWHWH1 tWHWH2 tVPEL Min. 200 0 100 80 30 6 0 40 0 100 60 0 0 140 60 10 9.5 1.0 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns s s ns ns ns ns ns ns ns ns s ms s
Notes: *1. Read timing parameters during Write/Erase operations are the same as during read only operations. Refer to AC characteristics for Main Memory Read Cycle. *2. Rise/Fall time 5 ns. *3. The integrated stop timer terminates the Write/Erase operations, thereby eliminating the need for a maximum specification.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE/ERASE PERFORMANCE *1
Rating Chip Erase Time Chip Write Time Write/Erase Cycle Notes *1 Min. -- -- 100,000 Typ. 1.0 *2 2.0 *2 -- Max. 10 12.5 *3 -- Unit Sec. Sec. Cycle
Notes: *1. Excludes 00H writing prior to Erasure. *2. TA = 25C, VPP = 12 V, 100,000 Cycles. *3. Minimum byte writing time excluding system overhead is 16 s (10 s program + 6 s write recovery), while maximum is 400 s/byte. (16 s x 25 loops allowed by algorithm).
ATTRIBUTE MEMORY WRITE CYCLE *1
Parameter Write Cycle Time Address Set Up Time Card Enable Set Up Time Output Enable Set Up Time Write Pulse Width Address Hold Time Data Set Up Time Data Hold Time Card Enable Hold Time Output Enable Hold Time Write Recovery Time End of Write to Output Time Number of Write per Byte Write Enable Hold Time Symbol tRWR tRAS tRCS tROES tRWP tRAH tRDS tRDH tRCH tROEH tRRE tRRBO N tRWEH Min. -- 20 0 20 100 50 50 20 0 20 50 -- 10000 10 Max. 10 -- -- -- -- -- -- -- -- -- -- 100 -- -- Unit ms ns ns ns ns ns ns ns ns ns ns ns Times ns
Note: *1. This parameter is for MB98A808A3, 809A3, 810A3, and 811A3.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
WRITE CYCLE 1: CE2 = VIH: x 8-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRM COMMAND
PROGRAMMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS Address VIH (A0, A18, A19, A20) VIL VIH CE1 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D0 to D7 VIL High-Z
DATA IN = 40H
tWC tAH
tWC
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH1
tWHGL
tCHZ tOE
tWP tDH tDS tDS
tWP tDH tOLZ tOH
DATA IN
DATA IN = C0H
VALID DATA
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Note: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
WRITE CYCLE 2: CE1 = VIH: x 8-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRAM COMMAND
PROGRAMMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS Address*2 VIH (A0, A18, A19, A20) VIL VIH CE2 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D8 to D15 VIL High-Z
DATA IN = 40H
tWC tAH
tWC
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH1
tWHGL
tCHZ
tOE tWP tDH tDS tDS
DATA IN = C0H
tWP tDH tOLZ tOH
VALID DATA
DATA IN
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
WRITE CYCLE 3: CE1 = CE2: x 16-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRAM COMMAND
PROGRAMMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS VIH Address*2 (A0, A18, A19, A20) VIL VIH CE1 = CE2 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D0 to D15 VIL High-Z
DATA IN = 4040H
tWC tAH
tWC
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH1
tWHGL
tCHZ
tOE tWP tDH tDS tDS
DATA IN = C0C0H
tWP tDH tOLZ tOH
VALID DATA
DATA IN
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
WRITE CYCLE 4: CE2 = VIH: x 8-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRAM COMMAND
PROGRAMMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS Address VIH (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE1 VIL tCP tDH tDS VIH D0 to D7 VIL High-Z
DATA IN = 40H
tWC tAH
tWC
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH1
tWHGL
tOHZ
tCP tDH tDS tDS
tCP tDH tOLZ
DATA IN = C0H
tOE
tCHZ tOH
VALID DATA
DATA IN
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Note: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
WRITE CYCLE 5: CE1 = VIH: x 8-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRAM COMMAND
PROGRAMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS VIH Address *2 (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE2 VIL tCP tDH tDS VIH D8 to D15 VIL High-Z
DATA IN = 40H
tWC tAH
tWC
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH1
tWHGL
tOHZ
tCP tDH tDS tDS
tCP tDH tOLZ
DATA IN = C0H
tOE
tCHZ tOH
VALID DATA
DATA IN
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
WRITE CYCLE 6: CE1 = CE2: x 16-bit Bus Organization
PROGRAM COMMAND LATCH ADDRESS & DATA
SETUP PROGRAM COMMAND
PROGRAMMING
PROGRAM VERIFY COMMAND
PROGRAM VERIFY
Address VIH (A1 to A17) VIL tWC tAS VIH Address*2 (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE1 = CE2 VIL tCP tDH tDS VIH D0 to D15 VIL High-Z
DATA IN = 4040H
tWC tAH
tWC
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH1
tWHGL
tOHZ
tCP tDH tDS tDS
tCP tDH tOLZ
DATA IN = C0C0H
tOE
tCHZ tOH
VALID DATA
DATA IN
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during programming command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
ERASE CYCLE 1: CE2 = VIH: x 8-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS Address VIH (A0, A18, A19, A20) VIL VIH CE1 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D0 to D7 VIL tVPEL 12 V VPP VPPL : Undefined High-Z
DATA IN = 20H
tWC tAH
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH2
tWHGL
tCHZ
tOE tWP tDH tDS
DATA IN = 20H
tWP tDH tDS
DATA IN = A0H
tOLZ tOH
VALID DATA
tCLZ tCE
Note: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
ERASE CYCLE 2: CE1 = VIH: x 8-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS Address*2 VIH (A0, A18, A19, A20) VIL VIH CE2 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D8 to D15 VIL tVPEL 12 V VPP VPPL : Undefined High-Z
DATA IN = 20H
tWC tAH
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH2
tWHGL
tCHZ
tWP tDH tDS
DATA IN = 20H
tWP tDH tDS tOLZ
DATA IN = A0H
tOE tOH
VALID DATA
tCLZ tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED) *1
ERASE CYCLE 3: CE1 = CE2: x 16-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS VIH Address*2 (A0, A18, A19, A20) VIL VIH CE1 = CE2 VIL tCS VIH OE VIL tGHWL tWPH VIH WE VIL tWP tDH tDS VIH D0 to D15 VIL tVPEL 12 V VPP VPPL : Undefined High-Z
DATA IN = 2020H
tWC tAH
tRC
tCH
tCS
tCH
tCS
tCH
tOHZ
tWHWH2
tWHGL
tCHZ
tWP tDH tDS
DATA IN = 2020H
tWP tDH tDS tOLZ
DATA IN = A0A0H
tOE tOH
VALID DATA
tCLZ tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
ERASE CYCLE 4: CE2 = VIH: x 8-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS Address VIH (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE1 VIL tCP tDH tDS VIH D0 to D7 VIL High-Z
DATA IN = 20H
tWC tAH
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH2
tWHGL
tOHZ
tCP tDH tDS
DATA IN = 20H
tCP tDH tDS
DATA IN = A0H
tOE tOLZ
tCHZ tOH
VALID DATA
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Note: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
ERASE CYCLE 5: CE1 = VIH: x 8-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS VIH Address *2 (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE2 VIL tCP tDH tDS VIH D8 to D15 VIL High-Z
DATA IN = 20H
tWC tAH
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH2
tWHGL
tOHZ
tCP tDH tDS
DATA IN = 20H
tCP tDH tDS
DATA IN = A0H
tOE tOLZ
tCHZ tOH
VALID DATA
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED) *1
ERASE CYCLE 6: CE1 = CE2: x 16-bit Bus Organization
SETUP ERASE COMMAND
ERASE COMMAND
ERASING
ERASE VERIFY COMMAND
ERASE VERIFY
Address VIH (A1 to A17) VIL tWC tWC tAS Address*2 VIH (A0, A18, A19, A20) VIL VIH WE VIL tWS VIH OE VIL tGHWL tCPH VIH CE1 = CE2 VIL tCP tDH tDS VIH D0 to D15 VIL High-Z
DATA IN = 2020H
tWC tAH
tRC
tWH
tWS
tWH
tWS
tWH
tWHWH2
tWHGL
tOHZ
tCP tDH tDS
DATA IN = 2020H
tCP tDH tDS
DATA IN = A0A0H
tOE tOLZ
tCHZ tOH
VALID DATA
tCLZ tVPEL 12 V VPP VPPL : Undefined tCE
Notes: *1. A0, A18, A19 and A20 have to be fixed during erase command input because these addresses are chip decoding addresses. Refer to the WRITE/ERASE CHIP DECODING INFORMATION. *2. A0 = Either VIL or VIH.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 1: CE2 = VIH: x 8-bit Bus Organization
Address (A0 to A11)
VIH VIL tRAS tRCS tRAH tRCH VIH
CE1 VIL tROES VIH OE VIL tRWEH VIH WE VIL tRDS VIH D0 to D7 VIL tRWR VOH D7 *2 VOL High-Z tRRBO High-Z tRDH tRRE High-Z tRWP tROEH
DATA VALID
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3, and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. Data polling operation.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 2: CE1 = CE2: x 16-bit Bus Organization
Address (A0 to A11)
VIH VIL tRAS tRCS VIH tRAH tRCH
CE1 = CE2 VIL tROES VIH OE VIL tRWEH VIH WE VIL tRDS VIH D0 to D7 *2 VIL tRWR VOH D7 *3 VOL High-Z tRRBO High-Z tRDH tRRE High-Z tRWP tROEH
DATA VALID
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3, and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. H-level or L-level is output from D8 to D15. *3. Data polling operation.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 3: CE2 = VIH: x 8-bit Bus Organization
Address (A0 to A11)
VIH VIL tRAS tRAH tRWP VIH tRWEH
CE1 VIL tROES VIH OE VIL tRCS VIH WE VIL tRDS VIH D0 to D7 VIL High-Z DATA VALID tRWR VOH D7 *2 VOL High-Z tRRBO tRDH tRRE High-Z tRCH tROEH
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3 and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. Data polling operation.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 4: CE1 = CE2: x 16-bit Bus Organization
Address (A0 to A11)
VIH VIL tRAS tRAH tRWP VIH tRWEH
CE1 = CE2 VIL tROES VIH OE VIL tRCS VIH WE VIL tRDS VIH D0 to D7 *2 VIL tRWR VOH D7 *3 VOL High-Z tRRBO High-Z tRDH tRRE High-Z tRCH tROEH
DATA VALID
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A808A3, 809A3, 810A3, and 811A3. "FF" data is available on MB98A808A2, 809A2, 810A2, and 811A2 only. *2. H-level or L-level is output from D8 to D15. *3. Data polling operation.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s WRITE/ERASE INFORMATION
Fig. 4 - WRITE FLOWCHART FOR 8-BIT ORGANIZATION
START VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPH GS
VPPH = 12.0 V 0.6 V VPPL 6.5 V S: START ADDRESS G: ADDRESS N: STOP ADDRESS X: COUNTER VALUE
X1
WRITE SETUP COMMAND = 40H WRITE DATA TO CARD TIME OUT (10 s) WRITE VERIFY COMMAND = C0H TIME OUT (6 s) READ DATA FROM CARD NO NO
VERIFY DATA YES G=G+1 NO G = N? YES READ COMMAND = 00H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL END
X = 25? YES
X=X+1
READ COMMAND = 00H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL ERROR
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
Fig. 5 - WRITE FLOWCHART FOR 16-BIT ORGANIZATION
START VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPH GS XE 1, XO 1, Y 0 WRITE SETUP COMMAND = 4040H (when Y = 0) = FF40H (when Y = 1) = 40FFH (when Y = 2) WRITE DATA TO CARD = WDWDH (when Y = 0) = FFWDH (when Y = 1) = WDFFH (when Y = 2) TIME OUT (10 s) WRITE VERIFY COMMAND = C0C0H (when Y = 0) = 00C0H (when Y = 1) = C000H (when Y = 2) TIME OUT (6 s) READ DATA FROM CARD NO Y = 0, XE = XE + 1 XO = XO + 1 NO UPPER BYTE? NO LOWER BYTE? NO VERIFY DATA YES G=G+2 NO G = N? YES READ COMMAND = 0000H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL END READ COMMAND = 0000H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL ERROR XE = 25? or XO = 25? YES YES Y= 2 XO = XO + 1 YES Y=1 XE = XE + 1 VPPH = 12.0 V 0.6 V VPPL 6.5 V S: START ADDRESS G: ADDRESS N: STOP ADDRESS XO: ODD BYTE COUNTER VALUE XE: EVEN BYTE COUNTER VALUE Y: PROGRAMMING FLAG
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
Fig. 6 - ERASE FLOWCHART FOR 8-BIT ORGANIZATION
START VPPH = 12.0 V 0.6 V VPPL 6.5 V G: ADDRESS N1: LOWER BYTE END ADDRESS N2: UPPER BYTE END ADDRESS X: COUNTER VALUE VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPH WRITE 00H TO CARD
ALL DATA = 00H?
LOWER BYTE ERASE ADDRESS SET UP (A0 = 0) X1 ERASE SETUP COMMAND = 20H ERASE COMMAND = 20H TIME OUT (10 s) ERASE VERIFY COMMAND = A0H TIME OUT (6 s) READ DATA FROM CARD NO
X=X+1 NO YES
DATA= FFH? YES G=G+2 NO G = N1? YES
X = 3000?
1 (Continued on page 41.)
2 (Continued on page 41.)
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
Fig. 7 - ERASE FLOWCHART FOR 8-BIT ORGANIZATION (Continued)
(Continued from page 40.) VPPH = 12.0 V 0.6 V VPPL 6.5 V G: ADDRESS N1: LOWER BYTE END ADDRESS N2: UPPER BYTE END ADDRESS X: COUNTER VALUE 1
(Continued from page 40.) 2
UPPER BYTE ERASE ADDRESS SETUP (A0 = 1) X1
ERASE SETUP COMMAND = 20H ERASE COMMAND = 20H TIME OUT (10 ms) ERASE VERIFY COMMAND = A0H TIME OUT (6 s) READ DATA FROM CARD NO
X=X+1 NO
DATA = FFH? YES G=G+2 NO G = N2? YES READ COMMAND = 00H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL END
X = 3000?
YES
READ COMMAND = 00H VCC = 5.0 V 0.25 V VPP1 = VPP2 = VPPL ERROR
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
Fig. 8 - ERASE FLOWCHART FOR 16-BIT ORGANIZATION
START VCC, VPP1 = VPP2 = VPPH WRITE 0000H TO CARD VCC = 5.0 V 0.25 V VPPH = 12.0 V 0.6 V VPPL 6.5 V G: ADDRESS N: STOP ADDRESS XO: ODD BYTE COUNTER VALUE XE: EVEN BYTE COUNTER VALUE Y: ERASING FLAG
DATA = 0000H?
ERASE ADDRESS SETUP XE 1, XO 1, Y 0
ERASE SETUP COMMAND = 2020H (when Y = 0) = FF20H (when Y = 1) = 20FFH (when Y = 2) ERASE COMMAND
= 2020H (when Y = 0) = FF20H (when Y = 1) = 20FFH (when Y = 2)
TIME OUT (10 s)
Y = 0, XE = XE + 1 XO = XO + 1 NO UPPER BYTE? NO LOWER BYTE? YES Y=2 XO = XO + 1 YES Y=1 XE = XE + 1
ERASE VERIFY COMMAND = A0A0H (when Y = 0) = 00A0H (when Y = 1) = A000H (when Y = 2) TIME OUT (6 s) READ DATA FROM CARD NO
NO XE= 3000? or XO= 3000? YES
DATA = FFFFH? YES G=G+2 NO G = N? YES READ COMMAND = 0000H VCC, VPP1 = VPP2 = VPPL END
READ COMMAND = 0000H VCC, VPP1 = VPP2 = VPPL ERROR
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s UNIQUE FEATURES FOR FLASH MEMORY CARD
1. SPECIAL MONITORING PINS
VCC CD1
1.1 CD1, CD2: Card Detection Pins These pins detect the insertion of the card into the system. (See Fig. 9.) When the memory card has been correctly inserted, CD1 and CD2 are detected by the system. CD1, CD2 are tied to ground on the card side as shown in Fig. 9.
(A)
VCC CD2 (B) system side card side
- Fig. 9 -
1.2 WP: Write Protect Pins This pin monitors the position of the Write Protect switch. As shown in Fig. 10, the Flash memory card has a Write Protect switch at the top of the card. To write to the card, the switch must be turned to the "Non Protect" position and the WE pin low. L-level is output on the WP pin. To prevent writing to the card, the switch must be turned to the "Protect" position. H-level is output on the WP pin.
Non Protect Protect Flash Memory Card Write Protect Switch
WP Switch Protect Non Protect
WP (output) H L
- Fig. 10 -
s DEVICE HANDLING PRECAUTIONS
This device in composed of fine electronic parts, so take care in handling or keeping it as below. * The card is made fine, so do not keep it in the high temperature nor high humiditly, place like in the direct sunshine nor near the heater. * The card should not be bent, scratched, dropped nor be shocked violently. * This device should never be taken a part. It could destroy the card or your personal computer hardware. * To help you handle this device safely, request us the device specifications when purchasing this device.
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
s PACKAGE DIMENSIONS
68-PIN MEMORY CARD (CASE No.: CRD-68P-M17)
Dimensions comform with PCMCIA/JEIDA. (PC CARD STANDARD 95)
2-R1.00(.039) 1.600.05 (.063.002) 1.000.05 (.039.002) 41.91 (1.650) REF 1.000.05 (.039.002) "A" 1.000.05 (.039.002)
85.600.20(3.370.008) 10.50(.413)
54.000.10 (2.126.004)
14.50 (.571)
10.50(.413) 3.300.10(.130.004) CONNECTOR PORTION 3.300.20(.130.008) CARD BODY
Details of "A" part 1.270.10(.050.004)TYP.
1PIN 1.270.10 (.050.004)
C
1994 FUJITSU LIMITED K68017SC-2-2
Dimensions in mm (inches)
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MB98A808Ax-/809Ax-/810Ax-/811Ax-20
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9704 (c) FUJITSU LIMITED Printed in Japan
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